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73K302L Bell 212A, 103, 202 Single-Chip Modem
April 2000
DESCRIPTION
The 73K302L is a highly integrated single-chip modem IC which provides the functions needed to construct a Bell 202, 212A and 103 compatible modem. The 73K302L is an enhancement of the 73K212L single-chip modem with Bell 202 mode features added. The 73K302L is capable of 1200 or 0-300 bit/s full-duplex operation over dial-up lines. 4-wire full-duplex capability and a low speed back channel are also provided in Bell 202 mode. The 73K302L recognizes and generates a 900 Hz soft carrier turn-off tone, and allows 103 for 300 bit/s FSK operation. The 73K302L integrates analog, digital, and switched-capacitor array functions on a single substrate, offering excellent performance and a high level of functional integration in a single 28-pin DIP or PLCC package. The 73K302L operates from a single +5V supply with very low power consumption. The 73K302L includes the DPSK and FSK modulator/demodulator functions, call progress and handshake tone monitors, test modes, and a tone generator capable of producing DTMF, answer, and 900 Hz soft carrier turn-off tone. This device supports Bell 202, 212A and 103 modes of operation, allowing both synchronous and
(continued)
FEATURES
* * * * * * * * * * *
One-chip Bell 212A, 103 and 202S/T standard compatible modem data pump Full-duplex operation at 0-300 bit/s (FSK), 1200 bit/s (DPSK) or 0-1200 bit/s (FSK) forward channel with or without 0-150 bit/s back channel Full-duplex 4-wire operation in Bell 202 mode Pin and software compatible with other TDK Semiconductor Corporation K-Series 1-chip modems Interfaces directly with standard microprocessors (8048, 80C51 typical) Serial port for data transfer Both synchronous and asynchronous modes of operation Call progress, carrier, precise answer tone (2225 Hz), soft carrier turn-off (SCT), and FSK mark detectors DTMF, answer, and SCT tone generators Test modes available: ALB, DL, RDL, Mark, Space, Alternating bit patterns CMOS technology for low power consumption using 60 mW @ 5V from a single power supply
BLOCK DIAGRAM
AD0-AD7 DATA BUS BUFFER 8-BIT BUS FOR RD WR ALE CS RESET READ WRITE CONTROL LOGIC CONTROL AND STATUS DIGITAL PROCESSING PSK MODULATOR/ DEMODULATOR FSK MODULATOR/ DEMODULATOR DTMF & TONE GENERATORS
TRANSMIT FILTER RECEIVE FILTER
TXA
RXA
INT
STATUS AND CONTROL LOGIC
TXD RXD
SERIAL PORT FOR DATA
TESTS: ALB, DLB RDLB PATTERNS CLOCK GENERATOR
SMART DIALING & DETECT FUNCTIONS
POWER
RXCLK
EXCLK
TXCLK CLK
XTL1
XTL2
GND VREF VDD ISET
73K302L Bell 212A, 103, 202 Single-Chip Modem
DESCRIPTION (continued)
asynchronous communications. The 73K302L is designed to appear to the systems designer as a microprocessor peripheral, and will easily interface with popular one-chip microprocessors (80C51 typical) for control of modem functions through its 8bit multiplexed address/data bus or via an optional serial command bus. An ALE control line simplifies address demultiplexing. Data communications occurs through a separate serial port only. The 73K302L is ideal for use in either free standing or integral system modem products where multistandard data communications is desired. Its high functionality, low power consumption and efficient packaging simplify design requirements and increase system reliability. A complete modem requires only the addition of the phone line interface, a modem controller, and RS232 level converter for a typical system. Tri-mode capability in one-chip allows full-duplex Bell 212 and 103 operation or assymetrical Bell 202S operation over the 2-wire switched telephone network. 202T mode full-duplex operation at 1200 bit/s is also possible when operating on 4-wire leased lines. A soft carrier turn-off feature facilitates fast line turn around when using the 202S mode for half-duplex applications. The 73K302L is part of TDK Semiconduct K- Series family of pin and function compatible single-chip modem products. These devices allow systems to be configured for higher speeds and Bell or CCITT operation with only a single component change. The SYNC/ASYNC converter also has an extended overspeed mode which allows selection of an output overspeed range of either +1% or +2.3%. In the extended overspeed mode, stop bits are output at 7/8 the normal width. The serial data stream from the transmit buffer or the rate converter is passed through the data scrambler and onto the analog modulator. The data scrambler can be bypassed under processor control when unscrambled data must be transmitted. If serial input data contains a break signal through one character (including start and stop bits) the break will be extended to at least 2 times N + 3 bits long (where N is the number of transmitted bits/character). Serial data from the demodulator is passed first through the data descrambler and then through the SYNC/ASYNC converter. The ASYNC/ASYNC converter will reinsert any deleted stop bits and output data at an intra-character rate (bit-to-bit timing) of no greater than 1219 bit/s. An incoming break signal (low through two characters) will be passed through without incorrectly inserting a stop bit. SYNCHRONOUS MODE The Bell 212A standard defines synchronous operation at 1200 bit/s. Operation is similar to that of the asynchronous mode except that data must be synchronized to a provided clock and no variation in data transfer rate is allowable. Serial input data appearing at TXD must be valid on the rising edge of TXCLK. TXCLK is an internally derived signal in internal mode and is connected internally to the RXCLK pin in slave mode. Receive data at the RXD pin is clocked out on the falling edge of RXCLK. The ASYNCH/SYNCH converter is bypassed when synchronous mode is selected and data is transmitted out at the same rate as it is input. DPSK MODULATOR/DEMODULATOR In DPSK mode the 73K302L modulates a serial bit stream into di-bit pairs that are represented by four possible phase shifts as prescribed by the Bell 212A standards. The base-band signal is then filtered to reduce intersymbol interference on the bandlimited 2-wire telephone line. Transmission occurs using either a 1200 Hz (originate mode) or 2400 Hz (answer mode) carrier. Demodulation is the reverse of the modulation process, with the incoming analog
OPERATION
ASYNCHRONOUS MODE Data transmission for the DPSK mode requires that data ultimately be transmitted in a synchronous fashion. The 73K302L includes ASYNC/SYNC and SYNC/ASYNC converters which delete or insert stop bits in order to transmit data at a regular rate. In asynchronous mode the serial data comes from the TXD pin into the ASYNC/SYNC converter. The ASYNC/SYNC converter accepts the data provided on the TXD pin which normally must be 1200 bit/s +1.0%, 2.5%. The rate converter will then insert or delete stop bits in order to output a signal which is 1200 bit/s .01% (0.01% is the required synchronous data rate accuracy). 2
73K302L Bell 212A, 103, 202 Single-Chip Modem
signal eventually decoded into di-bits and converted back to a serial bit stream. The demodulator also recovers the clock which was encoded into the analog signal during modulation. Demodulation occurs using either a 1200 Hz carrier (answer mode or ALB originate mode) or a 2400 Hz carrier (originate mode or ALB answer mode). The 73K302L uses a phase locked loop coherent demodulation technique for optimum receiver performance. FSK MODULATOR/DEMODULATOR The FSK modulator produces a frequency modulated analog output signal using two discrete frequencies to represent the binary data. Bell 103 mode uses 1270 and 1070 Hz (originate, mark and space) or 2225 and 2025 Hz (answer, mark and space). Bell 202 mode uses 1200 Hz (mark) and 2200 Hz (space for the main channel and 387 Hz (mark) and 487 Hz (space) for the back channel. The modulation rate of the back channel is up to 150 baud. Demodulation involves detecting the received frequencies and decoding them into the appropriate binary value. The rate converter and scrambler/descrambler are automatically bypassed in the 103 or 202 modes. PASSBAND FILTERS AND EQUALIZERS High and low band filters are included to shape the amplitude and phase response of the transmit and receive signals and provide compromise delay equalization and rejection of out-of-band signals in the receive channel. Amplitude and phase equalization are necessary to compensate for distortion of the transmission line and to reduce intersymbol interference in the bandlimited receive signal. The transmit signal filtering approximates a 75% square root of raised Cosine frequency response characteristic. AGC The automatic gain control maintains a signal level at the input to the demodulators which is constant to within 1 dB. It corrects quickly for increases in signal which would cause clipping and provides a total receiver dynamic range of >45 dB. PARALLEL BUS INTERFACE Four 8-bit registers are provided for control, option select and status monitoring. These registers are addressed with the AD0, AD1, and AD2 multiplexed address lines (latched by ALE) and appear to a control microprocessor as four consecutive memory locations. Two control registers and the tone register are read/write memory. The detect register is read only and cannot be modified except by modem response to monitored parameters. SERIAL COMMAND INTERFACE MODE The serial command interface allows access to the 73K302L control and status registers via a serial command port. In this mode the AD0, AD1 and AD2 lines provide register addresses for data passed through the data pin under control of the RD and WR lines. A read operation is initiated when the RD line is taken low. The first bit is available after RD is brought low and the next seven cycles of EXCLK will then transfer out seven bits of the selected address location LSB first. A write takes place by shifting in eight bits of data LSB first for eight consecutive cycles of EXCLK. WR is then pulsed low and data transfer into the selected register occurs on the rising edge of WR. SPECIAL DETECT CIRCUITRY The special detect circuitry monitors the received analog signal to determine status or presence of carrier, answer tone and weak received signal (long loop condition), special tones such as FSK marking and the 900 Hz soft carrier turn-off tone are also detected. A highly frequency selective call progress detector provides adequate discrimination to accurately detect lower quality call progress signals. DTMF GENERATOR The DTMF generator will output one of 16 standard tone pairs determined by a 4-bit binary value and TX DTMF mode bit previously loaded into the tone register. Tone generation is initiated when the DTMF mode is selected using the tone register and the transmit enable (CR0 bit D1) is changed from 0 to 1. SOFT CARRIER TURN-OFF TONE GENERATOR The soft carrier turn-off tone generator will output a 900 Hz tone. When activated in Bell 202 main channel transmit mode, the output signal will shift to 900 Hz, maintaining phase continuity during the transition.
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73K302L Bell 212A, 103, 202 Single-Chip Modem
PIN DESCRIPTION
POWER NAME GND VDD VREF ISET PLCC/PIN DIP NUMBER 28 15 26 24 TYPE I I O I DESCRIPTION System Ground. Power supply input, 5V 10%. Bypass with 0.1 and 22 F capacitors to GND. An internally generated reference voltage. Bypass with 0.1 F capacitor to GND. Chip current reference. Sets bias current for op-amps. The chip current is set by connecting this pin to VDD through a 2 M resistor. ISET should be bypassed to GND with a 0.1 F capacitor.
PARALLEL MICROPROCESSOR INTERFACE ALE AD0-AD7
CS
12 4-11 20
I I/O I
Address latch enable. The falling edge of ALE latches the address on AD0-AD2 and the chip select on CS. Address/data bus. These bidirectional tri-state multi-plexed lines carry information to and from the internal registers. Chip select. A low on this pin during the falling edge of ALE allows a read cycle or a write cycle to occur. AD0-AD7 will not be driven and no registers will be written if CS (latched) is not active. The state of CS is latched on the falling edge of ALE. Output clock. This pin is selectable under processor control to be either the crystal frequency (for use as a processor clock) or 16 times the data rate for use as a baud rate clock in DPSK mode only. The pin defaults to the crystal frequency on reset. Interrupt. This open drain output signal is used to inform the processor that a detect flag has occurred. The processor must then read the detect register to determine which detect triggered the interrupt. INT will stay low until the processor reads the detect register or does a full reset. Read. A low requests a read of the 73K302L internal registers. Data cannot be output unless both RD and the latched CS are active or low. Reset. An active high signal on this pin will put the chip into an inactive state. All control register bits (CR0, CR1, Tone) will be reset. The output of the CLK pin will be set to the crystal frequency. An internal pull down resistor permits power on reset using a capacitor to VDD.
CLK
1
O
INT
17
O
RD
14 25
I I
RESET
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73K302L Bell 212A, 103, 202 Single-Chip Modem
PARALLEL MICROPROCESSOR INTERFACE (continued) NAME
WR
PLCC/PIN DIP NUMBER 13
TYPE I
DESCRIPTION Write. A low on this informs the 73K302L that data is available on AD0-AD7 for writing into an internal register. Data is latched on the rising edge of WR. No data is written unless both WR and the latched CS are active low.
SERIAL MICROPROCESSOR INTERFACE A0-A2 DATA 46 11 I I/O Register Address Selection. These lines carry register addresses and should be valid during any read or write operation. Serial Control Data. Data for a read/write operation is clocked in or out on the falling edge of the EXCLK pin. The direction of data flow is controlled by the RD pin. RD low outputs data. RD high inputs data. Read. A low on this input informs the 73K302L that data or status information is being read by the processor. The falling edge of the RD signal will initiate a read from the addressed register. The RD signal must continue for eight falling edges of EXCLK in order to read all eight bits of the referenced register. Read data is provided LSB first. Data will not be output unless the RD signal is active. Write. A low on this input informs the 73K302L that data or status information has been shifted in through the DATA pin and is available for writing to an internal register. The normal procedure for a write is to shift in data LSB first on the DATA pin for eight consecutive falling edges of EXCLK and then to pulse WR low. Data is written on the rising edge of WR.
RD
14
I
WR
13
I
Note:
The serial control mode is provided by tying ALE high and CS low. In this configuration AD7 becomes the data input and AD0, AD1 and AD2 become the address only. See the SERIAL CONTROL TIMING diagram on page22
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73K302L Bell 212A, 103, 202 Single-Chip Modem
PIN DESCRIPTION (continued)
DTE USER INTERFACE NAME EXCLK PLCC/PIN DIP NUMBER 19 TYPE I DESCRIPTION External Clock. This signal is used only in synchronous DPSK transmission when the external timing option has been selected. In the external timing mode the rising edge of EXCLK is used to strobe synchronous DPSK transmit data available on the TXD pin. Also used for serial control interface. Receive Clock. The falling edge of this clock output is coincident with the transitions in the serial received DPSK data output. The rising edge of RXCLK can be used to latch the valid output data. RXCLK will be valid as long as a carrier is present. In Bell 202 mode a clock which is 16 times 1200 or 16 times 150 baud data rate is output. Received Data Output. Serial receive data is available on this pin. The data is always valid on the rising edge of RXCLK when in synchronous mode. RXD will output constant marks if no carrier is detected. Transmit Clock.This signal is used only in synchronous DPSK transmission to latch serial input data on the TXD pin. Data must be provided so that valid data is available on the rising edge of the TXCLK. The transmit clock is derived from different sources depending upon the synchronization mode selection. In Internal Mode the clock is 1200 Hz generated internally. In External Mode TXCLK is phase locked to the EXCLK pin. In Slave Mode TXCLK is phase locked to the RXCLK pin. TXCLK is always active. In Bell 202 mode the output is a 16 times 1200 baud clock or 16 times 150 baud to drive a UART. Transmit Data Input. Serial data for transmission is applied on this pin. In synchronous modes, the data must be valid on the rising edge of the TXCLK clock. In asynchronous modes (1200 or 300 baud) no clocking is necessary. DPSK must be 1200 bit/s +1%, -2.5% or +2.3%, -2.5% in extended overspeed mode.
RXCLK
23
O
RXD
22
O/ Weak Pull-up
TXCLK
18
O
TXD
21
I
ANALOG INTERFACE AND OSCILLATOR RXA TXA XTL1 XTL2 27 16 2 3 I O I I Received modulated analog signal input from the telephone line interface. Transmit analog output to the telephone line interface. These pins are for the internal crystal oscillator requiring a 11.0592 MHz parallel mode crystal and two load capacitors to Ground. XTL2 can also be driven from an external clock.
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73K302L Bell 212A, 103, 202 Single-Chip Modem
REGISTER DESCRIPTIONS Four 8-bit internal registers are accessible for control and status monitoring. The registers are accessed in read or write operations by addressing the A0 and A1 address lines in serial mode, or the AD0 and AD1 lines in parallel mode. The AD0 and AD1 lines are latched by ALE. Register CR0 controls the method by which data is transferred over the phone line. CR1 controls the interface between the microprocessor and the 73K302L internal state. DR is a detect register which provides an indication of monitored modem status conditions. TR, the tone control register, controls the DTMF generator, answer and guard tones and RXD output gate used in the modem initial connect sequence. All registers are read/write except for DR which is read only. Register control and status bits are identified below:
REGISTER BIT SUMMARY
ADDRESS REGISTER CONTROL REGISTER 0 CONTROL REGISTER 1 DETECT REGISTER AD2 - AD0 D7 MODULATION OPTION TRANSMIT PATTERN 1 D6 0 D5 TRANSMIT MODE 3 ENABLE DETECT INTERRUPT RECEIVE DATA TRANSMIT ANSWER TONE DATA BIT NUMBER D4 TRANSMIT MODE 2 BYPASS SCRAMBLER/ ADD PH. EQ. 202 UNSCR. MARKS D3 TRANSMIT MODE 1 CLK CONTROL D2 TRANSMIT MODE 0 RESET D1 TRANSMIT ENABLE TEST MODE 1 CALL PROGRESS D0 ANSWER/ ORIGINATE TEST MODE 0 LONG LOOP DTMF0/ SPEC. TONE/ ANSWER TONE/ SELECT X
CR0
000
CR1
001
TRANSMIT PATTERN 0
DR
010
X
X
CARRIER DETECT
SPECIAL TONE DTMF/ 202T FDX
TONE CONTROL REGISTER ID REGISTER
TR
011
RXD OUTPUT CONTROL
TRANSMIT SCT TONE
TRANSMIT DTMF
DTMF3
DTMF1/ OVERSPEED
ID
110
ID
ID
ID
ID
X
X
X
NOTE: When a register containing reserved control bits is written into, the reserved bits must be programmed as 0's. X = Undefined, mask in software.
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73K302L Bell 212A, 103, 202 Single-Chip Modem
REGISTER ADDRESS TABLE
ADDRESS REGISTER AD2 - AD0 D7 D6 D5 DATA BIT NUMBER D4 D3 D2 D1 D0
CONTROL REGISTER 0
CR0
000
MODULATION OPTION
0
TRANSMIT MODE 3
TRANSMIT MODE 2
TRANSMIT MODE 1
TRANSMIT MODE 0
TRANSMIT ENABLE
ORIGINATE/ ANSWER
0=103 FSK 1=202 FSK
0000=PWR DOWN 1100=FSK 0010=EXT SYNCH 0011=SLAVE SYNCH 0100=ASYNCH 8 BITS/CHAR 0101=ASYNCH 9 BITS/CHAR 0110=ASYNCH 10 BITS/CHAR 0111=ASYNCH 11 BITS/CHAR 1100=FSK BELL 103 OR 202 TRANSMIT PATTERN 0 ENABLE DETECT INTERRUPT BYPASS SCRAMBLER/ ADD PH. EQ. CLK CONTROL
0=DISABLE TXA OUTPUT 1=ENABLE TXA OUTPUT
IN 212, 103 MODES: 0=ANSWER 1=ORIGINATE IN 202 MODE: 0=RECEIVE @ 1200 BIT/S, TRANSMIT @ 150 BIT/S 1=RECEIVE @ 150 BIT/S, TRANSMIT @ 1200 BIT/S TEST MODE 0
CONTROL REGISTER 1
CR1
001
TRANSMIT PATTERN 1
RESET
TEST MODE 1
00=TX DATA 01=TX ALTERNATE 10=TX MARK 11=TX SPACE
0=DISABLE 1=ENABLE
0=NORMAL 1=BYPASS SCRAMBLER 1=ADD EXTRA PHASE EQ. IN 202 ONLY UNSCR. MARK
0=XTAL 1=16 X DATA RATE OUTPUT AT CLK PIN IN DPSK MODE ONLY CARRIER DETECT
0=NORMAL 1=RESET
00=NORMAL 01=ANALOG LOOPBACK 10=REMOTE DIGITAL LOOPBACK 11=LOCAL DIGITAL LOOPBACK CALL PROGRESS LONG LOOP
DETECT REGISTER
DR
010
X
X
RECEIVE DATA
SPECIAL TONE
OUTPUTS RECEIVED DATA STREAM TONE CONTROL REGISTER RXD OUTPUT CONTROL RXD PIN 0=NORMAL 1=TRI STATE TRANSMIT SCT TONE 0=OFF 1=ON TRANSMIT ANSWER TONE 0=OFF 1=ON TRANSMIT DTMF
0=CONDITION NOT DETECTED 1=CONDITION DETECTED
TR
011
DTMF3
DTMF2/ 202T FDX
DTMF1/ OVERSPEED
DTMF0/ SPECIAL TONE
0=DATA 1=TX DTMF
4 BIT CODE FOR 1 OF 16 DUAL TONE COMBINATIONS.0=1% 1=2.5% 0=NORMAL 1=FULL DUPLEX IN 202 MODE
0=900 HZ SCT TONE IF IN ANSWER MODE =2225 HZ ANSWER TONE IN 103 OR 212 ORIGINATE MODES 1=FSK MARK
ID REGISTER
10
110
ID
ID
ID
ID
X
X
X
X
00XX=73K212AL, 322L, 321L 01XX=73K221AL, 302L 10XX=73K222AL, 222BL 1100=73K224L 1110=73K324L 1100=73K224BL 1110=73K324BL
X = Undefined, mask in software 0 = Only write zeros to this location
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73K302L Bell 212A, 103, 202 Single-Chip Modem
CONTROL REGISTER 0
D7 CR0 000 MODUL. OPTION D6 0 D5 TRANSMIT MODE 3 D4 TRANSMIT MODE 2 D3 TRANSMIT MODE 1 D2 TRANSMIT MODE 0 D1 TRANSMIT ENABLE D0 ANSWER/ ORIGINATE
BIT NO. D0
NAME Answer/ Originate
CONDITION 0
DESCRIPTION Selects answer mode in 103 and 212A modes (transmit in high band, receive in low band) or in Bell 202 mode, receive at 1200 bit/s and transmit at 150 bit/s. Selects originate mode in 103 and 212A modes (transmit in low band, receive in high band) or in Bell 202 mode, receive at 150 bit/s and transmit at 1200 bit/s. Note: This bit works with TR bit D0 to program special tones detected in Tone Register. See detect and tone registers.
1
D1
Transmit Enable
0 1
Disables transmit output at TXA. Enables transmit output at TXA. Note: Answer tone and DTMF TX control require TX enable.
D5, D4,D3, D2
Transmit Mode
D5 D4 D3 D2 0 0 0 0 0 0 0 1 Selects power down mode. All functions disabled except digital interface. Internal synchronous mode. In this mode TXCLK is an internally derived 1200 Hz signal. Serial input data appearing at TXD must be valid on the rising edge of TXCLK. Receive data is clocked out of RXD on the falling edge of RXCLK. External synchronous mode. Operation is identical to internal synchronous, but TXCLK is connected internally to EXCLK pin, and a 1200 Hz 0.01% clock must be supplied externally. Slave synchronous mode. Same operation as other synchronous modes. TXCLK is connected internally to the RXCLK pin in this mode. Selects DPSK asynchronous mode - 8 bits/character (1 start bit, 6 data bits, 1 stop bit). Selects DPSK asynchronous mode - 9 bits/character (1 start bit, 7 data bits, 1 stop bit). Selects DPSK asynchronous mode - 10 bits/character (1 start bit, 8 data bits, 1 stop bit). Selects DPSK asynchronous mode - 11 bits/character (1 start bit, 8 data bits, Parity and 1 or 2 stop bits). Selects 103 or 202 FSK operation.
0
0
1
0
0
0
1
1
0 0 0 0 1
1 1 1 1 1
0 0 1 1 0
0 1 0 1 0
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73K302L Bell 212A, 103, 202 Single-Chip Modem
CONTROL REGISTER 0 (continued)
D7 CR0 000 MODUL. OPTION D6 0 D5 TRANSMIT MODE 3 D4 TRANSMIT MODE 2 D3 TRANSMIT MODE 1 D2 TRANSMIT MODE 0 D1 TRANSMIT ENABLE D0 ANSWER/ ORIGINATE
BIT NO. D6 D7
NAME Modulation Option
CONDITION 0 D7 X 0 1 D5 0 1 1 D4 X 1 1
DESCRIPTION Not used; must be written as a "0." Selects: DPSK asynchronous mode at 1200 bit/s. FSK Bell 103 mode. FSK Bell 202 mode.
CONTROL REGISTER 1
D7 CR1 001 TRANSMIT PATTERN 1 D6 TRANSMIT PATTERN 0 D5 ENABLE DETECT INTER. D4 BYPASS SCRAMB/ ADD PH. EQ. D3 CLK CONTROL D2 RESET D1 TEST MODE 1 D0 TEST MODE 0
BIT NO. D1, D0
NAME Test Mode
CONDITION D1 0 0 D0 0 1
DESCRIPTION Selects normal operating mode. Analog loopback mode. Loops the transmitted analog signal back to the receiver, and causes the receiver to use the same center frequency as the transmitter. To squelch the TXA pin, transmit enable must be forced low. Not supported in FDX202 mode. Selects remote digital loopback. Received data is looped back to transmit data internally, and RXD is forced to a mark. Data on TXD is ignored. Selects local digital loopback. Internally loops TXD back to RXD and continues to transmit carrier from TXA pin. Selects normal operation. Resets modem to power down state. All control register bits (CR0, CR1, Tone) are reset to zero. The output of the CLK pin will be set to the crystal frequency.
1
0
1 D2 Reset 0 1
1
10
73K302L Bell 212A, 103, 202 Single-Chip Modem
CONTROL REGISTER 1 (continued)
D7 CR1 001 TRANSMIT PATTERN 1 D6 TRANSMIT PATTERN 0 D5 ENABLE DETECT INTER. D4 BYPASS SCRAMB/ ADD PH. EQ. D3 CLK CONTROL D2 RESET D1 TEST MODE 1 D0 TEST MODE 0
BIT NO. D3
NAME CLK Control
CONDITION 0 1
DESCRIPTION Selects 11.0592 MHz crystal echo output at CLK pin. Selects 16 times the data rate, output at CLK pin in DPSK modes only. Selects normal operation. DPSK data is passed through scrambler. Selects Scrambler Bypass. DPSK data is routed around scrambler in the transmit path. In Bell 202 mode, additional phase equalization is added to the main channel filters when D4 is set to 1. Disables interrupt at INT pin. Enables INT output. An interrupt will be generated with a change in status of DR bits D1-D4. The special tone and call progress detect interrupts are masked when the TX enable bit is set. Carrier detect is masked when TX DTMF is activated. All interrupts will be disabled if the device is in power down mode.
D4*
Bypass Scrambler/ Add Phase Equalization
0 1
D5
Enable Detect
0 1
D7, D6
Transmit Pattern
D7 0 0 1 1
D6 0 1 0 1 Selects normal data transmission as controlled by the state of the TXD pin. Selects an alternating mark/space transmit pattern for modem testing. Selects a constant mark transmit pattern. Selects a constant space transmit pattern.
* D4 should always be set to 1 when receiving 1200 bit/s data and to 0 when transmitting 1200 bit/s data in 202 mode.
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73K302L Bell 212A, 103, 202 Single-Chip Modem
DETECT REGISTER
D7 DR 010 X D6 X D5 RECEIVE DATA D4 UNSCR. MARK D3 CARR. DETECT D2 SPECIAL TONE D1 CALL PROG. D0 LONG LOOP
BIT NO. D0 D1
NAME Long Loop Call Progress Detect
CONDITION 0 1 0 1
DESCRIPTION Indicates normal received signal. Indicates low received signal level. No call progress tone detected. Indicates presence of call progress tones. The call progress detection circuitry is activated by energy in the normal 350 to 620 Hz call progress band. No special tone detected as programmed by CR0 bit D0 and Tone Register bit D0. Special tone detected. The detected tone is: (1) 2225 Hz answer tone if D0 of TR=0 and the device is in Bell 103 or 212A originate mode. (2) Soft carrier turn-off tone if D0 of TR=0 and the device is in Bell 202 answer mode. (3) An FSK mark in the mode the device is set to receive if D0 of TR is set to 1. Tolerance on special tones is 3%.
D2
Special Tone Detect
0 1
D3
Carrier Detect Unscrambled Mark Detect
0 1 0 1
No carrier detected in the receive channel. Indicated carrier has been detected in the received channel. No unscrambled mark. (DPSK only) Indicates detection of unscrambled marks in the received data. A valid indication requires that unscrambled marks be received for > 165.5 6.5 ms. Continuously outputs the received data stream. This data is the same as that output on the RXD pin, but it is not disabled when RXD is tri-stated.
D4
D5
Receive Data
D6, D7
Not Used
Undefined
Mask in software
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73K302L Bell 212A, 103, 202 Single-Chip Modem
TONE REGISTER
D7 TR 011 RXD OUTPUT CONTR. D6 TRANSMIT SOFT CARRIER TURN-OFF TONE D5 TRANSMIT ANSWER TONE D4 TRANSMIT DTMF D3 DTMF 3 D2 DTMF 2/ 202 FDX D1 DTMF 1/ OVERSPEED D0 DTMF 0/ SPECIAL TONE SEL
BIT NO. D0
NAME DTMF 0/ Special Tone Detect/Select
CONDITION D5 0 0 D4 1 0 D0 X 0
DESCRIPTION D0 interacts with bits D5, D4, and CR0 as shown. Transmit DTMF tones. 2225 Hz answer tone will be detected in D2 of DR if originate mode is selected in CR0. 900 Hz SCT tone will be detected in D2 of DR if Bell 202 answer mode is selected in CR0.
X 1 1 D4 D1 D2 D3, D2, D1, D0 DTMF 1/ Overspeed DTMF2/202T FDX DTMF 3, 2, 1, 0 0 0
0 0 0
1 0 1 D1 0 1
Mark of an FSK mode selected in CR0 is to be detected in D2 of DR. 2225 Hz answer tone will be generated when in answer mode and transmit enable is selected in CR0. 2100 Hz answer tone will be generated when in answer mode and transmit enable is selected in CR0. D1 interacts with D4 as shown. Asynchronous DPSK 1200 bit/s +1.0% -2.5%. Asynchronous DPSK 1200 bit/s +2.3% -2.5%. Enables 202 half-duplex operation if TR D4 = 0 Enables 202 full-duplex operation if TR D4 = 0
0 1 D3 D2 D1 D0 0 1 0 1 0 1 01
Programs 1 of 16 DTMF tone pairs that will be transmitted when TX DTMF and TX enable bit (CR0, bit D1) are set. Tone encoding is shown below: KEYBOARD EQUIVALENT 1 2 3 4 5 6 7 8 9 0 13 DTMF CODE D3 D2 D1 D0 0 0 0 0 0 0 0 1 1 1 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 TONES LOW HIGH 697 697 697 770 770 770 852 852 852 941 1209 1336 1477 1209 1336 1477 1209 1336 1477 1336
73K302L Bell 212A, 103, 202 Single-Chip Modem
TONE REGISTER (continued)
D7 TR 011 RXD OUTPUT CONTR. D6 TRANSMIT SOFT CARRIER TURN-OFF TONE D5 TRANSMIT ANSWER TONE D4 TRANSMIT DTMF D3 DTMF 3 D2 DTMF 2/ 202 FDX D1 DTMF 1/ OVERSPEED D0 DTMF 0/ SPECIAL TONE SEL
BIT NO. D3, D2, D1, D0(cont.)
NAME
CONDITION
DESCRIPTION KEYBOARD EQUIVALENT * # A B C D DTMF CODE D3 D2 D1 D0 1 1 1 1 1 0 0 1 1 1 1 0 1 0 0 1 1 0 1 0 1 0 1 0 TONES LOW HIGH 941 941 697 770 852 941 1209 1477 1633 1633 1633 1633
D4
Transmit DTMF
0 1
Disable DTMF. Activate DTMF. The selected DTMF tones are transmitted continuously when this bit is high. TX DTMF overrides all other transmit functions. Disables answer tone generator. Enables answer tone generator. A 2225 Hz answer tone will be transmitted continuously when the transmit enable bit is set. To transmit answer tone, the device must be in answer mode. Disables SCT tone generator. Transmit SCT tone in Bell 202 mode. To transmit SCT tone, 202 originate mode must be selected. Enables RXD pin. Receive data will be output on RXD. Disables RXD pin. The RXD pin reverts to a high impedance with internal weak pull-up resistor.
D5
Transmit Answer Tone
0 1
D6
Transmit SCT Tone RXD Output Control
0 1 0 1
D7
Notes for Tone Register use: 1. To detect SCT tone, 202 answer mode must be selected. 2. For answer tone detection, 103 or 212 originate mode must be active. To transmit answer tone, the 73K302L must be in 103 or 212 answer mode. 3. After completion of DTMF dialing, bit D2 should be reset unless 202 full-duplex mode is selected.
14
73K302L Bell 212A, 103, 202 Single-Chip Modem
ID REGISTER
ID 110 D7 ID D6 ID D5 ID D4 ID D3 X D2 X D1 X D0 X
BIT NO. D7, D6, D5, D4
NAME Device Identification Signature 0 0 1 1 1 1 1
CONDITION D7 D6 D5 D4 0 1 0 1 1 1 1 X X X 0 1 0 1 X X X 0 0 0 0
DESCRIPTION Indicates Device: 73K212AL, 73K321L or 73K322L 73K221AL or 73K302L 73K222AL , 73K222BL 73K224L 73K324L 73K224BL 73K324B L Mask in software
D3-D0
Not Used
Undefined
15
73K302L Bell 212A, 103, 202 Single-Chip Modem
ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS PARAMETER VDD Supply Voltage Storage Temperature Soldering Temperature (10 sec.) Applied Voltage RATING 7V -65 to 150C 260C -0.3 to VDD+0.3V
Note: All inputs and outputs are protected from static charge using built-in, industry standard protection devices and all outputs are short-circuit protected. RECOMMENDED OPERATING CONDITIONS PARAMETER VDD Supply voltage TA, Operating Free-Air Temp. Clock Variation
(11.0592 MHz) Crystal or external clock
CONDITION
MIN 4.5 -40 -0.01
NOM 5
MAX 5.5 +85 +0.01
UNIT V C %
External Components (Refer to Application section for placement.) VREF Bypass Capacitor Bias setting resistor ISET Bypass Capacitor VDD Bypass Capacitor 1 VDD Bypass Capacitor 2 XTL1 Load Capacitor XTL2 Load Capacitor (External to GND)
(Placed between VDD and ISET pins)
0.1 1.8 0.1 0.1 22 40 20 2 2.2
F M F F F pF
(ISET pin to GND) (External to GND) (External to GND) Depends on crystal characteristics; from pin to GND
16
73K302L Bell 212A, 103, 202 Single-Chip Modem
DC ELECTRICAL CHARACTERISTICS (TA = -40C to 85C, VDD = recommended range unless otherwise noted.) PARAMETER IDD, Supply Current IDDA, Active IDD1, Power-down IDD2, Power-down Digital Inputs VIH, Input High Voltage Reset, XTL1, XTL2 All other inputs VIL, Input Low Voltage IIH, Input High Current IIL, Input Low Current Reset Pull-down Current Input Capacitance Digital Outputs VOH, Output High Voltage VOL, Output Low Voltage VOL, CLK Output RXD Tri-State Pull-up Curr. CMAX, CLK Output Capacitance Inputs XTL1, 2 Load Capacitors CLK Capacitance, all Digital Input pins Depends on crystal Maximum Capacitive Load 15 10 60 15 pF pF pF IOH MIN = -0.4 mA IO MAX = 1.6 mA IO = 3.6 mA RXD = GND Maximum Capacitive Load -1 2.4 VDD 0.4 0.6 -50 15 V V V A pF VI = VIH Max VI = VIL Min Reset = VDD All Digital Input Pins -200 1 50 10 3.0 2.0 0 VDD VDD 0.8 100 V V V A A A pF CONDITION ISET Resistor = 2 M CLK = 11.0592 MHz CLK = 11.0592 MHz CLK = 19.200 kHz 8 12 4 3 mA mA mA MIN NOM MAX UNIT
17
73K302L Bell 212A, 103, 202 Single-Chip Modem
ELECTRICAL SPECIFICATIONS (continued)
DYNAMIC CHARACTERISTICS AND TIMING (TA = -40C to +85C, VDD = recommended range unless otherwise noted.) PARAMETER DPSK Modulator Carrier Suppression Output Amplitude FSK Modulator Output Freq. Error Transmit Level Soft Carrier Turnoff Tone Harmonic Distortion in 700-2900 Hz band Output Bias Distortion Total Output Jitter DTMF Generator Freq. Accuracy
Output Amplitude, Low group Output Amplitude, High group
CONDITION Measured at TXA TX scrambled marks CLK = 11.0592 MHz Transmit Dotting Pattern THD in the alternate band DPSK or FSK Transmit Dotting Pattern In ALB @ RXD Random Input in ALB @ RXD Must not be in 202 mode
MIN 45 -11.5 -0.35 -11.5 -11.9
NOM
MAX
UNIT dB
-10
-9 +0.35
dBm0 % dBm0 dBm0 dB %
-10 -10.9 -60 3
-9 -9.9 -50
-10 -0.25
+10 +0.25 -9 -7 2.0 45 -8 -6 3.0 -28
% % dBm0 dBm0 dB dBm0 dB
DPSK mode DPSK mode High-Band to Low-Band With Sinusoid Refer to Performance Curves
-10 -8 1.0 -38
Twist Long Loop Detect Dynamic Range Note:
Parameters expressed in dBm0 refer to the following definition: 0 dB loss in the Transmit path from TXA to the telephone line. 2 dB gain in the Receive path from the telephone line to RXA. Refer to the Basic Box Modem diagram in the Applications section for the DAA design.
18
73K302L Bell 212A, 103, 202 Single-Chip Modem
DYNAMIC CHARACTERISTICS AND TIMING (continued) PARAMETER Call Progress Detector Detect Level Reject Level Delay Time Hold Time Hysteresis Carrier Detect Threshold Delay Time Bell 103 Bell 212A Bell 202 Forward Channel Bell 202 Back Channel Hold Time Bell 103 Bell 212A Bell 202 Forward Channel Bell 202 Back Channel Hysteresis Special Tone Detectors Detect Level Delay Time Answer tone 900 Hz SCT tone 202 Main Channel Mark 202 Back Channel Mark 1270 or 2225 Hz marks * If SCT duration >4ms, it is guaranteed to detect. Preceded by valid carrier* 10 4 10 20 10 25 10 25 65 25 ms ms ms ms ms See definitions for TR bit D0 mode -49 -42 dBm0 6 10 3 10 2 20 24 8 25 ms ms ms ms dB 8 15 6 25 20 32 12 40 ms ms ms ms DPSK or FSK receive data -49 -42 dBm0 -3 dB points in 285 and 675 Hz Test signal is a 460 Hz sinusoid -70 dBm0 to -30 dBm0 STEP -30 dBm0 to -70 dBm0 STEP 20 20 2 -38 -45 40 40 dBm0 dBm0 ms ms dB CONDITION MIN NOM MAX UNIT
19
73K302L Bell 212A, 103, 202 Single-Chip Modem
DYNAMIC CHARACTERISTICS AND TIMING (continued) PARAMETER Special Tone Detectors (continued) Hold Time Answer tone 900 Hz SCT tone 202 Main Channel Mark 202 Back Channel Mark 1270 or 2225 Hz marks Hysteresis Detect Freq. Range Output Smoothing Filter Output Load TXA pin; FSK Single Tone out for THD = -50 dB in 0.3 to 3.4 kHz Frequency >12 kHz in all modes See Transmit Energy Spectrum TXA pin TXA pin; 76.8 kHz or 122.88 kHz in 202 main channel Originate or Answer -10 Hz to +10 Hz Carrier Frequency Change % of data rate (center at 1200 Hz) Analog data in at RXA pin to receive data valid at RXD pin DTMF or FSK tones
For DTMF, must not be in 202 mode
CONDITION
MIN
NOM
MAX
UNIT
4 1 3 10 5 2 Any Special Tone -3 10
15 10 10 25 15 +3
ms ms ms ms ms dB % k
50 -60 20 0.1 50 0.4
pF dBm0 mVrms
Out of Band Energy Output Impedance Clock Noise Carrier VCO Capture Range Capture Time DPSK Recovered Clock Capture Range Data Delay Time Tone Generator Tone Accuracy Tone Level
-10 40
+10 100
Hz ms
-625 30
+625 50
ppm ms
-5 -1
+5 +1
Hz dB
20
73K302L Bell 212A, 103, 202 Single-Chip Modem
DYNAMIC CHARACTERISTICS AND TIMING PARALLEL CONTROL INTERFACE PARAMETER Timing (Refer to Timing Diagrams) TAL TLA TLC TCL TRD TLL TRDF TRW TWW TDW TWD TWW TRD TRDF TCKD TCKW TDCK TAC TCA TWH *
CS/ADDr. setup before ALE Low CS/ADDr. hold after ALE Low
CONDITION
MIN 15 20 30 -5
NOM
MAX
UNIT ns ns ns ns
ALE Low to RD/WR Low
RD/WR Control to ALE High
Data out from RD Low ALE width Data float after RD High
RD width WR width
140 30 90 200 140 40 25 140 25000 140 50 200 200 150 50 50 85
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Data setup before WR High Data hold after WR High
WR width
Data out from RD Low Data float after RD High Data out after EXCLK Low
WR after EXCLK Low
Write data setup before EXCLK Low Address setup before control* Address hold after control* Data hold after EXCLK
Control for setup is the falling edge of RD or WR. Control for hold is the falling edge of RD or the rising edge of WR.
NOTE: Asserting ALE, CS, and RD or WR concurrently can cause unintentional register accesses. When using non-8031 compatible processors, care must be taken to prevent this from occurring when designing the interface logic.
21
73K302L Bell 212A, 103, 202 Single-Chip Modem
TIMING DIAGRAMS
BUS TIMING DIAGRAM (PARALLEL VERSION)
TLL ALE TLC RD WR TLA TAL AD0-AD7 CS ADDRESS READ DATA ADDRESS TRD TRDF TDW WRITE DATA TWD TRW TCL TLC TWW
READ TIMING DIAGRAM (SERIAL MODE)
T1 EXCLK TRCLK RD TAR A0-A2 TRA T2
ADDRESS
TRD DATA D0 D1
TCKDR D2 D3 D4 D5 D6 D7
TRDF
WRITE TIMING DIAGRAM (SERIAL MODE)
T2 EXCLK T1 WR TCKW TAW A0-A2 ADDRESS TCKDW D1 D2 D3 D4 D5 D6 D7 TWA
TWW
TDCK DATA D0
Note: EXCLK must be Low to read D0 after RD is asserted. 22
73K302L Bell 212A, 103, 202 Single-Chip Modem
APPLICATIONS INFORMATION
GENERAL CONSIDERATIONS Figures 1 and 2 show basic circuit diagrams for K-Series modem integrated circuits. K-Series products are designed to be used in conjunction with a control processor, a UART or RS-232 serial data interface, and a DAA phone line interface to function as a typical intelligent modem. The K-Series ICs interface directly with Intel 8048 and 80C51 microprocessors for control and status monitoring purposes. Two typical DAA arrangements are shown: one for a split 5 or 12 volt design and one for a single 5V design. These diagrams are for reference only and do not represent productionready modem designs. K-Series devices are available with two control interface versions: one for a parallel multiplexed address/data interface, and one for a serial
C14 39 pF Y1 11.0592 MHZ C13 18 pF +5V
interface. The parallel version is intended for use with 8039/48 or 8031/51 microcontrollers from Intel or many other manufacturers. The serial interface can be used with other microcontrollers or in applications where only a limited number of port lines are available or the application does not lend itself to a multiplexed address/data interface. The parallel versions may also be used in the serial mode, as explained in the data sheet pin description. In most applications the controller will monitor the serial data for commands from the DTE and the received data for break signals from the far end modem. In this way, commands to the modem are sent over the same line as the transmitted data. In other applications the RS-232 interface handshake lines are used for modem control.
N/C
R10 2.2M XTL1 INT CLK INT XTL1 XTL2 VDD ISET GND RD WR ALE CS K-SERIES LOW POWER FAMILY VREF RXA C10 0.1 F C11 0.1 F
RS232 LEVEL CONVERTERS CA CB CC CD CF RTS CTS DSR DTR DCD
XTL2
C9 0.1 F
+
C8 22 F
C1 390 pF R5 37.4K R4 20K LM 1458
80C51 P1.0 P1.1 P1.2 P1.3 P1.5 P1.6 P0.0-7 RD WR ALE P3.1 P3.2
-
C6 0.1 F RXA
U1A C2 300 pF R7 43.2K C3 1000 pF
+
P3.0 P1.7 RESET BA BB DA DD DB TXD RXD EXCLK RXCLK TXCLK
R4 5.1K R3 3.6K
TXA C7 R6 0.1 F 20K RESET TXA +5V C12 1 F
V+ LM 1458 U1B + V-
U5, U6 MC145406
-
R1 475 1% D3, D4 4.7V ZENER C4 0.033 F
T1 MIDCOM 671-8005 C5 0.47 F 250V U2 4N35 D1 IN4004 +5V K1 D2 IN914 R9 10K +5 R8 22K
T
VR1 MOV V250L20
R Q1 2N2222A
22K
FIGURE 1: Basic Box Modem with Dual-Supply Hybrid
23
73K302L Bell 212A, 103, 202 Single-Chip Modem
APPLICATIONS INFORMATION (continued)
DIRECT ACCESS ARRANGEMENT (DAA) The telephone line interfaces show two examples of how the "hybrid" may be implemented. The split supply design (Figure 1) is a typical two op-amp hybrid. The receive op-amp serves two purposes. It supplies gain to amplify the receive signal to the proper level for the modem's detectors and demodulator, and it removes the transmitted signal from the receive signal present at the transformer. This is done by supplying a portion of the transmitted signal to the non-inverting input of the receive op-amp at the same amplitude as the signal appearing at the transformer, making the transmit signal common mode. The single-supply hybrid is more complex than the dual-supply version described above, but its use eliminates the need for a second power supply. This circuit (Figure 2) uses a bridged drive to allow undistorted signals to be sent with a single 5V supply. Because DTMF tones utilize a higher
C1 390 pF R4 37.4K 1% C3 0.1 F RXA R1 20K 1%
amplitude than data, these signals will clip if a single-ended drive approach is used. The bridged driver uses an extra op-amp (U1A) to invert the signal coming from the gain setting op-amp (U1B) before sending it to the other leg of the transformer. Each op-amp then supplies half the drive signal to the transformer. The receive amplifier (U1C) picks off its signal at the junction of the impedance matching resistor and the transformer. Because the bottom leg of the transformer is being driven in one direction by U1A and the resistor is driven in the opposite direction at the same time by U1B, the junction of the transformer and resistor remains relatively constant and the receive signal is unaffected. DESIGN CONSIDERATIONS TDK Semiconductor's 1-chip modem products include all basic modem functions. This makes these devices adaptable for use in a variety of applications, and as easy to control as conventional digital bus peripherals.
8
* U1C
+
9 10
C4 0.0047 F
R5 3.3K
R2 20K 1%
+5V 5 6
+ -
4
7
R3 475 1% T1 MIDCOM 671-8005
Note: Op-amp U1 must be rated for single 5V operation. R10 & R11 values depend on Op-amp
11
* U1B
R6 22.1K C6 0.1 F TXA R9 20K 1% R8 20K 1% 2 3 +5V VOLTAGE REFERENCE K1 R10* D4 IN914 D1 IN4004 R7 20K 1% C5 750 pF C2 0.033 F
C10 0.47 F 250V U2 4N35 R13 22K
+5V
T
D2 3.3V ZENERS D3 1 +5V
VR1 MOV V250L20
+
* U1A
R12 22K
R
R11*
C7 0.1 F
+
R14 10K
Q1 2N2222A
C8 10 F
HOOK RING
FIGURE 2: Single 5V Hybrid Version
24
73K302L Bell 212A, 103, 202 Single-Chip Modem
Unlike digital logic circuitry, modem designs must properly contend with precise frequency tolerances and very low level analog signals, to ensure acceptable performance. Using good analog circuit design practices will generally result in a sound design. Following are additional recommendations which should be taken into consideration when starting new designs.
MODEM PERFORMANCE CHARACTERISTICS
The curves presented here define modem IC performance under a variety of line conditions while inducing disturbances that are typical of those encountered during data transmission on public service telephone lines. Test data was taken using an AEA Electronics' "Autotest I" modem test set and line simulator, operating under computer control. All tests were run full-duplex, using a Concord Data Systems 224 as the reference modem. A 511 pseudo-random-bit pattern was used for each data point. Noise was Cmessage weighted and all signal-to-noise (S/N) ratios reflect total power measurements similar to the CCITT V.56 measurement specification. The individual tests are defined as follows.
CRYSTAL OSCILLATOR
The K-Series crystal oscillator requires a parallel mode (antiresonant) crystal which operates at 11.0592 MHz. It is important that this frequency be maintained to within 0.01% accuracy. In order for a parallel mode crystal to operate correctly and to specification, it must have a load capacitor connected to the junction of each of the crystal and internal inverter connections, terminated to ground. The values of these capacitors depend primarily on the crystal's characteristics, and to a lesser degree on the internal inverter circuit. The values used affect the accuracy and start up characteristics of the oscillator.
BER vs. S/N
This test measures the ability of the modem to operate over noisy lines with a minimum of data-transfer errors. Since some noise is generated in the best of dial-up lines, the modem must operate with the lowest S/N ratio possible. Better modem performance is indicated by test curves that are closest to the BER axis. A narrow spread between curves representing the four line parameters indicates minimal variation in performance while operating over a range of aberrant operating conditions. Typically, a DPSK modem will exhibit better BER-performance test curves receiving in the low band than in the high band.
LAYOUT CONSIDERATIONS
Good analog/digital design rules must be used to control system noise in order to obtain highest performance in modem designs. The more digital circuitry present on the PC board, the more this attention to noise control is needed. The modem should be treated as a high impedance analog device. A 22 F electrolytic capacitor in parallel with a 0.1 F ceramic capacitor between VDD and GND is recommended. Liberal use of ground planes and larger traces on power and ground are also highly favored. High speed digital circuits tend to generate a significant amount of EMI (Electro-Magnetic Interference) which must be minimized in order to meet regulatory agency limitations. To accomplish this, high speed digital devices should be locally bypassed, and the telephone line interface and K-Series device should be located close to each other near the area of the board where the phone line connection is accessed. To avoid problems, power supply and ground traces should be routed separately to the analog and digital functions on the board, and digital signals should not be routed near low level or high impedance analog traces. The analog and digital grounds should only connect at one point near the K-Series device ground pin to avoid ground loops. The K-Series modem IC's should have both high frequency and low frequency bypassing as close to the package as possible.
BER vs. Receive Level
This test measures the dynamic range of the modem. Because signal levels vary widely over dial-up lines, the widest possible dynamic range is desirable. The minimum Bell specification calls for 36 dB of dynamic range. S/N ratios are held constant at the indicated values while the receive level is lowered from a very high to very low signal levels. The width of the "bowl" of these curves, taken at the BER point, is the measure of dynamic range.
.
25
73K302L Bell 212A, 103, 202 Single-Chip Modem
73K302L BER vs S/N
10-2 10-2
HIGH BAND RECEIVE -30 dBm DPSK OPERATION 1200 bit/s
73K302L BER vs S/N
10-3
10-3
C2
BIT ERROR RATE
BIT ERROR RATE
C1 or 3002 FLAT
10-4
FLAT W/EQ. FLAT W/O EQ. C2 W/O EQ.
3002 W/O EQ.
10-4
10-5
10-5
RECEIVE LEVEL -30 dBm BELL 202 MODE
C2 W/EQ.
3002 W/EQ.
10-6 4 6 8 10 12 14 16
10-6 2 4 6 8 10 12 14
SIGNAL TO NOISE (dB)
SIGNAL TO NOISE (dB)
73K302L BER vs RECEIVE LEVEL
10-2
HIGH BAND RECEIVE DPSK OPERATION C2 LINE
73K302L BER vs PHASE JITTER
10-2
HIGH BAND RECEIVE DPSK OPERATION
10-3
10-3
BIT ERROR RATE
10-4
BIT ERROR RATE
10-4
3002 11.5 dB S/N
S/N = 10.8 dB
10-5
10-5
C2 10.8 dB S/N
S/N = 15 dB
10-6 10 0 -10 -20 -30 -40 -50
10-6 0 4 8 12 16 20 24
RECEIVE LEVEL (dBm)
PHASE JITTER (DEG.)
26
73K302L Bell 212A, 103, 202 Single-Chip Modem
73K302L BER vs CARRIER OFFSET
10-2
HIGH BAND RECEIVE DPSK OPERATION
10-3
BIT ERROR RATE
10-4
3002 11.8 dB S/N
C2 11.3 dB S/N
10-5
10-6 12 8 4 0 -4 -8 -12
CARRIER OFFSET (HZ)
27
73K302L Bell 212A, 103, 202 Single-Chip Modem
MECHANICAL SPECIFICATIONS
28-Pin DIP
28-Pin PLCC
0.495 (12.573) 0.485 (12.319)
0.075 (1.905) 0.065 (1.651)
PIN NO. 1 IDENT.
0.165 (4.191) 0.180 (4.572)
0.495 (12.573) 0.485 (12.319)
0.456 (11.650) 0.450 (11.430) 0.016 (0.406) 0.020 (0.508)
0.050 (1.270) 0.045 (1.140) 0.020 (0.508)
0.390 (9.906) 0.430 (10.922)
0.456 (11.650) 0.450 (11.430)
28
73K302L Bell 212A, 103, 202 Single-Chip Modem
PACKAGE PIN DESIGNATIONS
(Top View)
CLK XTL1 XTL2 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 ALE WR RD GND RXA VREF RESET ISET RXCLK RXD TXD CS EXCLK TXCLK INT TXA VDD
CAUTION: Use handling procedures necessary for a static sensitive component.
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
4 5 6 7 8 9 10 11
3
2
1
28 27 26 25 24
PLCC PINOUTS ARE THE SAME AS THE 28-PIN DIP
23 22 21 20 19
12 13 14 15 16 17 18
600 Mil 28-Pin DIP 73K302L-28-IP
28-Pin PLCC 73K302L-IH
ORDERING INFORMATION
PART DESCRIPTION 73K302L 28-Pin Plastic Dual-In-Line 28-Pin Plastic Leaded Chip Carrier 73K302L-IP 73K302L-IH 73K302L-IP 73K302L-IH ORDER NUMBER PACKAGING MARK
No responsibility is assumed by TDK Semiconductor Corporation for use of this product nor for any infringements of patents and trademarks or other rights of third parties resulting from its use. No license is granted under any patents, patent rights or trademarks of TDK Semiconductor Corporation and the company reserves the right to make changes in specifications at any time without notice. Accordingly, the reader is cautioned to verify that the data sheet is current before placing orders. TDK Semiconductor Corporation, 2642 Michelle Drive, Tustin, CA 92780-7019, (714) 508-8800, FAX: (714) 508-8877 Protected by the following patents: (4,777,453), (4,691,172 a1990 TDK Semiconductor Corporation 04/24/00- rev. D
29

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